1. Field of the Invention
This invention relates to a control unit and a multiplex communication system, and more particularly to a control unit for changing the frequency of a clock pulse for a CPU under a prescribed condition into a lower frequency, and a multiplex communication system for executing data communication between such control units connected to a bus line.
2. Description of the Related Art
An example of these control units is shown in FIG. 7. These control units are arranged, e.g. at various parts within a motor vehicle. These control units are connected to each other via a bus line (not shown) to constitute a multiplex communication system.
In FIG. 7, the control unit includes a CPU 10 for executing various kinds of processing or control according to a prescribed program, a ROM 20 which stores the program for the CPU 10 and an RAM 30 which stores various kinds of data and has an area necessary for the processing of the CPU 10.
The CPU 10 is connected to a high frequency oscillator 41 for producing a first clock pulse P1 which operates the CPU 10 at a first frequency and a low frequency oscillator 42 for producing a second clock pulse P2 which operates the CPU 10 at a second frequency lower than the first frequency.
The CPU 10 has functions of deciding that electric appliances within the vehicle are in a non-operating state when an ignition switch has been turned off and a door has been locked, and changing the clock pulse for operating the CPU 10 from the first clock pulse P1 into the second clock pulse P2, thereby shifting to a low electric power consumed state.
The moment that the CPU 10 itself shifts to the low electric power consumed state, it produces a signal requesting other control units to shift to the low electric power consumed state so that the entire multiplex communication system shifts to the low electric power consumed state.
When the CPU 10 detects door unlocking to decide that the electric appliances are in their usable state, it changes the clock pulse for operating itself from the second clock pulse P2 to the first clock pulse P1. Thus, the CPU 10 returns to the high speed processing state.
As described above, when the electric appliances have fallen into their non-used state, the control unit changes the clock pulse for operating the CPU 10 from the first clock pulse P1 at the high frequency into the second clock pulse P2 at the low frequency, thereby reducing power consumption and discharge of a battery.
Generally, the CPU 10 is provided with an output port Pout from which a port output signal S1 is periodically produced through the processing of the program operating within the CPU 10. A watchdog timer 50 serving as an outside monitoring means is connected to the output port Pout.
The watchdog timer 50 continuously monitors the port output signal S1 produced from the output port Pout. As a result of monitoring, if the watchdog timer 50 detects the abnormal state of the CPU 10 (specifically, the port output signal S1 is not detected for a prescribed time), it sends a reset signal S2 to a reset port Prst within the CPU 10.
In response to the reset signal S2, the CPU 10 intends to revert to its initial state to escape from the abnormal state. Therefore, when the CPU 10 has been fallen into the abnormal state such as “runaway”, in response to the reset signal S2 produced from the watchdog timer 50, the CPU 10 can revert to its initial state to escape from the abnormal state.
However, with the low frequency oscillator 42 being out of order, when the CPU 10 shifts to the low power consumed state, the CPU 10 becomes disabled. Then, the watchdog timer 50, under the decision that the disabling of the CPU 10 is abnormality, produces the reset signal S2. In response to the reset signal S2 thus produced, the CPU 10 reverts to the initial state and hence the high speed processing state again. Thereafter, the CPU 10 is changed into the low power consumed state. Thus, the processing of reverting to the low power consumed state, resetting and reverting to the high speed processing state will be repeated.
The control unit is so adapted that upon resetting, it produces, via a bus line, a signal requesting other control units to be reset. Therefore, whenever the resetting operation is executed, the low power consumed state of all the control units are released from the low power consumed state, and shift to the high speed processing state.
Namely, when at least one of the low frequency oscillators 40 within the control units which constitute a multiplex communication system becomes out of order, the entire multiplex communication system cannot be shifted to the low power consumed state. This does not reduce the power consumption, and in the worst case, leads to discharging of the battery. This also leads to the problem of disappearance of the information stored in the RAM due to the resetting operation.